VHDL中的FSM是Moore还是Mealy

Question

我正在用VHDL对FSM进行编码。特别地，它是一个同步序列检测器，在输入中有一个8位上的数字和一个"第一"，该"第一"必须仅在序列的第一个数字期间为"1"。输出由解锁和警告组成：如果序列(36，…(是正确的，则解锁="1"；如果序列是错误的，则警告="1(；如果序列的第一个数字不在，则第一个="1"。

在VHDL中，我使用两个进程，一个同步，另一个不同步。第二个简化版本是：

state_register_p : process(clk)
begin 
if (clk'EVENT and clk = '1') then
if(rst = '0') then
current_state <= S0;
errors_num <= "00";
five_cycles <= "000";
first_error <= '1';
else
current_state <= next_state;
if correct = '0' then
errors_num <= errors_num + "01";
else
errors_num <= "00";
end if;
end if;
end if;
end process state_register_p;
combinatorial_logic_p : process(current_state, num_in, first)
begin       
unlock <= '0';
warning <= '0';
case (current_state) is             
when S0 =>
if (to_integer(unsigned(num_in)) = 36) and (first = '1') then
next_state <= S1;
else
next_state <= S0;
when S1 =>
correct <= '0';
if (to_integer(unsigned(num_in)) = 19) and (first = '0') and errors_num /= "11" then
next_state <= S2;
elsif first = '1' or errors_num = "11" then
next_state <= S6;
else
next_state <= S0;
end if;
when S2 =>
correct <= '0';
if (to_integer(unsigned(num_in)) = 56)  and (first = '0') then
next_state <= S3;
elsif first = '1' then
next_state <= S6;
else
next_state <= S0;
end if;
when S3 =>
correct <= '0';
if (to_integer(unsigned(num_in)) = 101) and (first = '0') then
next_state <= S4;
elsif first = '1' then
next_state <= S6;
else
next_state <= S0;
end if;
when S4 =>
correct <= '0';
if (to_integer(unsigned(num_in)) = 73) and (first = '0') and (to_integer(unsigned(five_cycles)) = 5) then
next_state <= S5;
correct <= '1';
elsif first = '1' then
next_state <= S6;
else
next_state <= S0;
end if;
when S5 =>
correct <= '1';
if to_integer(unsigned(num_in)) = 36 and (first = '1') then
next_state <= S1;
else
next_state <= S0;
end if;
unlock <= '1';
when S6 =>
correct <= '0';
next_state <= S6; -- default, hold in current state
warning <= '1';
end case;               
end process combinatorial_logic_p;

通过在线阅读，我知道在Moore机器中，下一个状态仅取决于当前状态，因此输出仅在时钟边沿上变化，而在Mealy中，它也取决于输入，因此当输入变化时(即，不一定在时钟边沿(，其输出可能会变化。

在我的灵敏度列表中，我使用current_state和2个输入(num_In和first(，所以有可能说我在描述Mealy机器，还是因为我在等待下一个上升沿来更新输出，所以它仍然是Moore机器？

我仍然认为是摩尔，但我不确定。感谢

Answer 1

它是一个摩尔状态机，因为输出unlock和warning在combinatorial_logic_p过程中仅依赖于current_state。

注意，信号errors_num和five_cycles在combinatorial_logic_p处理中使用，但在灵敏度列表中被遗忘。因此，添加它们，或者如果使用VHDL-2008，则更改为(all)。